1. Field of the Invention
The present invention generally relates to semiconductor packaging. More particularly, the invention relates to processes and equipment used to package semiconductor devices to more efficiently account for residual devices.
2. Background Information
Integrated circuits are generally constructed on crystalline semiconductor substrates shaped as thin, circular wafers. A number of types of semiconductors can be used; however, doped silicon is by far the most popular semiconductor substrate in use today. Although the cost of the silicon dioxide used to prepare the silicon wafer is relatively low, the process for preparing a highly pure, properly-doped crystalline silicon wafer is both slow and expensive. As a result, the semiconductor industry has invested significant effort in efficient use of the silicon substrate.
Integrated circuits are multilayer electronic devices built on the surface of the wafer substrate through a series of cleaning, patterning, etching, deposition, and annealing operations. These steps serve to construct the functional features of the device, layer by layer. The surface area required by a given integrated circuit is a function of both the complexity of the design—i.e., the number and arrangement of individual transistors, capacitors, resistors and other electronic circuit elements—and the dimensions of each electronic element. In general, the footprint of individual integrated circuits is much smaller than the surface area of the wafer. Consequently, a single wafer can generally yield multiple—often even thousands—of integrated circuits.
Integrated circuits typically are created using wafer-level processing techniques, meaning that the semiconductor processing steps necessary to produce functional circuits (i.e., cleaning, patterning, etching, deposition, and annealing) are performed on an entire wafer. The arrangement of integrated circuits on a wafer surface is depicted in FIG. 1. Because of the resemblance to city maps, the spaces between devices are commonly termed “streets.” The streets are sacrificial areas reserved for cutting the wafer into the individual integrated circuits.
Referring still to FIG. 1, the single crystal wafers 11 used in semiconductor processing are not perfectly circular and instead have a flat portion 12 that allows proper orientation of the wafer crystal structure during processing and separation procedures. The integrated circuits 13 constructed on the wafer 11 are separated from one another by the grid of streets 14. Once the integrated circuits 13 are formed, the wafer II is placed on a film having a sticky surface. For obvious reasons, the film is generally referred to as “tacky film.” FIG. 2 shows a wafer 11 adhered to a tacky film 17, and in turn to a flex frame 18.
Following the processing steps, the individual integrated circuits, which are frequently referred to as “chips” or “dies,” must be separated from one another, optimally bonded to metal leads, and packaged in an appropriate ceramic or plastic housing. Chips typically are separated from one another on the wafer using a saw that cuts along the streets. The purpose of the tacky film 17 is to hold the individual integrated circuits in place during and after the separation step.
At some point after separation, the chips are placed into packing material to be delivered to an assembly process that electrically and mechanically bonds the chips to semiconductor packages or to printed circuit boards (PCBs). One common type of packing material is referred to as a “tape and reel” system. FIG. 3 shows a depiction of an exemplary tape and reel component delivery system 20. The tape and reel system generally comprises a carrier tape 22 and a cover tape 24 wound around a reel 26. The carrier tape includes numerous cavities 28 into which individual chips are placed. Once placed into a cavity 28, the chip is sealed in the cavity and protected by the cover tape 24. Specially designed pick and place machines individually pick chips from the tacky film and place them in cavities 28.
Not all of the chips formed on a wafer are necessarily acceptable devices. Some chips may suffer mechanical problems such as cracks and other chips may have electrical problems. For this reason, electrical and mechanical testing steps are performed as part of the manufacturing process. Those devices that fail the mechanical inspection are listed in a mechanical “map” and a similar map is created for those devices that fail an electrical test. Chips that are deemed unacceptable for customer use are termed “bad” chips. These maps also identify the good components (i.e., the devices that passed the mechanical and electrical tests). These maps are combined together into a single map. The single map identifies good and bad chips by their location relative to one or more reference points. The use of a typical good/bad map requires the wafer to have a set of physical reference markers (also called “alignment” markers) that identify a starting point for indexing the chips on the wafer. From this starting point, all of the chips are counted in a predefined order. The alignment markers may be special structures built into specific parts of the wafer or special devices contained thereon. In some cases, a set of dedicated units referred to as “mirror dies” are used to form shapes that can be clearly identified.
The identification of the alignment markers on the wafer and subsequent sequencing through the devices is generally performed by computer programmed machines with cameras, visual pattern recognition capabilities and other features which enable the machine to quickly and accurately pick the devices from the wafer. Once the wafer is aligned in the pick and place tool so that the tool is aware of the starting point, the tool accesses the good/bad map to determine the identity of the good and bad chips. The tool then picks the good chips, one at a time, and places the good chips on the carrier tape. Armed with the identity of the bad chips from the map, the tool skips over the bad units. Once the good devices have been picked off the wafer, the remaining bad device can be discarded.
Customers generally require each reel to have an exact and predetermined number of chips (e.g., 1000, 3000, 5000). A wafer on tacky film is loaded into a pick and place machine and aligned therein. A reel with carrier tape also is loaded into the machine. The pick and place tool then begins picking good units from the wafer and placing them into the tape. A wafer includes a certain number of good units that generally differs from the capacity of a single reel. For example, a particular wafer may have 20,500 total chips of which 20,100 are good (400 chips are bad). Further, the customer may require reels having exactly 3000 chips each. In this example, six complete reels can be filled with good chips leaving the partially picked wafer with 2100 good chips and 400 bad chips. The six reels of good chips then are delivered to the next part of the assembly process in which the chips are individually packaged or assembled.
The issue then becomes what to do with the remaining partially picked wafer still having a significant number of good chips (2100). Ideally, it would be desirable to save the chips on the tacky film and use the partially picked wafer to combine with the next build of that same chip. However, tacky film typically has a relatively short useful life of only a few days. After that, it becomes very difficult to pick the chips from the film without damaging the chips. Further, the chip manufacturer may not have an order of that same chip for several weeks or even longer. By that time, the previously partially picked wafer is unusable because of the limited useful life of the tacky film.
Another problem exists as well. In conventional packaging processes, the good chips are picked from the tacky film in the order they are listed in the map. In so doing, it is very likely that the alignment markers on the wafer will be disturbed. Once the alignment markers are disturbed, it is impossible to realign the wafer. As discussed above, the map identifies to the system the good chips and the bad chips in reference to a starting point. The identification of the starting point requires the wafer to be precisely aligned. If the wafer cannot be aligned, the system cannot use the map to discern the good from the bad chips on the wafer. Accordingly, a partially picked wafer, such as that described above in the example, cannot be reused in the pick and place machine even if the tacky film could last long enough. This is because, once the alignment markers are disturbed, there will be no way to install the partially picked wafer on tackv film in the machine during the next manufacturing run of the chip and align the wafer to permit the good/bad map to be used.
Often, the residual good and bad chips are used internally by the semiconductor manufacturer for engineering development purposes. It would be preferable, however, to be able to use the residual good chips for customer sales. Accordingly, a solution to this problem is needed.